1. Field of the Invention
The invention relates generally to a circuit configuration and method of manufacturing a transient voltage suppressor (TVS). More particularly, this invention relates to an improved circuit configuration and method of manufacturing an improved transient voltage suppressor (TVS) for low voltage protection by implementing a bottom source NMOS triggered Zener clamp configuration in the TVS circuit.
2. Description of the Relevant Art
The transient voltage suppressors (TVS) are commonly applied for protecting integrated circuits from damages due to the inadvertent occurrence of an over voltage imposed onto the integrated circuit. An integrated circuit is designed to operate over a normal range of voltages. However, in situations such as electrostatic discharge (ESD), electrical fast transients and secondary lightning, an unexpected and an uncontrollable high voltage may accidentally strike onto the circuit. The TVS devices are required to serve the protection functions to circumvent the damages that are likely to occur to the integrated circuits when such over voltage conditions occur. As increasing number of devices are implemented with the integrated circuits that are vulnerable to over voltage damages, demands for TVS protection are also increased. Exemplary applications of TVS can be found in the USB power and data line protection, Digital video interface, high speed Ethernet, Notebook computers, monitors and flat panel displays.
FIG. 1A shows a typical commercially available two-channel TVS array 10. There are two sets of steering diodes, i.e., diodes 15-H and 15-L and 20-H and 20-L respectively for each of the two input/output (I/Os) terminals I/O-1 and I/O-2. Furthermore, there is a Zener diode, i.e., diode 30, with a larger size to function as an avalanche diode from the high voltage terminal, i.e., terminal Vcc, to the ground voltage terminal, i.e., terminal Gnd. The high side diodes 15-H and 20-H provide a forward bias and are clamped by the large Vcc-Gnd diodes, e.g., the Zener diode 30, when a positive over-voltage strikes on one of the I/O or Vcc pads. The steering diodes 15-H, and 15-L and 20-H and 20-L are designed with a small size to reduce the I/O capacitance and thereby reducing the insertion loss in high-speed lines such as fast Ethernet applications. FIG. 1B shows the reverse current IR versus reverse blocking voltage VBR characteristics of the two-channel TVS Diode Array between the Vcc and the ground voltage of the TVS 10 shown in FIG. 1A. The reverse current IR as that shown in the diagram of FIG. 1B represents a reverse current conducted through the Zener diode, i.e., between Vcc and GND. Here it is assumed that the reverse BV of each steering diode is higher than the reverse BV of the Zener diode. But note that at high currents when the Vcc to Gnd pad voltage is equal or higher than the summation of the reverse BV of the steering diodes then the current would also flow through all the two series steering diode paths. Since the Zener diode has higher resistance per unit area compared with bipolar junction transistors (BJT) or silicon controlled rectifiers (SCR), this is actually a disadvantage at higher currents because the steering diodes also have to be rugged in reverse conduction. In the case of the SCR the Zener clamp voltage is lower at higher currents and hence the steering diodes paths will not conduct. The breakdown voltage of the Vcc-Gnd diode 30 and the steering diodes 15 and 20 should be greater than the operating voltage (Vrwm) so that these diodes only turn-on during the voltage transients. The problem with the Vcc-Gnd clamp diodes is that typically these diodes are very resistive in reverse conduction mode and require large area to reduce resistance. As shown in FIG. 1B, the high resistance leads to the increase of BV at high current. This is not desirable as high BV not only causes the break down of steering diodes as described above but also causes damage to the circuit the TVS device intends to protect. The requirement to have large diode size thus limits further miniaturization of a device when such TVS circuit is implemented.
One common method used in the integrated circuits to circumvent this drawback is to use a Zener triggered NPN as the clamp device as that shown in FIG. 2A. The TVS circuit 50 shown in FIG. 2A comprises a NPN bipolar transistor 55 connected in parallel to a Zener diode 60 to function as a Zener triggered NPN bipolar TVS device. FIG. 2B shows a current-voltage (IV) diagram for the Zener triggered NPN diode device. FIG. 2B illustrates that the TVS circuit begins conducting when the breakdown voltage of the Zener diode 60 is reached. When the base-emitter voltage is high enough, the NPN bipolar turns-on and snaps back to a lower voltage called the BVceo or holding voltage where BVceo stands for collector to emitter breakdown voltage with base left open. However, in a device that implements a TVS circuit, the snapback phenomenon is not desirable. The snap-back creates a sudden drop of the reverse voltage that often causes the circuit oscillations due to negative resistance, and can even drop into the operating voltage range, which is undesirable.
In order to resolve the snap-back difficulties, commonly owned patent application Ser. No. 11/444,555 was previously submitted on May 31, 2006, and issued May 26, 2009 as U.S. Pat. No. 7,538,997. The disclosures made in that Application are hereby incorporated by reference in this Patent Application. The TVS circuits as described in the patent application Ser. No. 11/444,555 are implemented to protect a device operated at a voltage of approximately five volts and are useful for 5V device protection. However, in addition to the technical difficulties related to the sudden large voltage drops as discussed above, there is a need to reduce the transient voltage protection at a further reduced voltage such as 3.3 volts. The TVS circuits disclosed have been effective to protective circuit operated at about five volts, however, would not provide the required protection when the operational voltage is further reduced below five volts because of its high triggering and clamping voltage.
In another co-pending patent application Ser. No. 11/712,317 previously submitted on Feb. 28, 2007 by a common inventor of this application further disclosed another new TVS circuit to provide an improved clamping at a further reduced voltage such that TVS protection can be provided for devices operated 3.3 to 5 volts with low leakage implemented by stacking PMOS diodes. The TVS protection circuit disclosed in that Application includes a MOS triggering TVS with tunable low snap-back voltage wherein the MOS-SCR is operated without a negative resistance while providing good clamping factor. The TVS protection circuit further includes high side diodes with NBL to suppress the I/O-to-I/O latch-up such that the device performance is further improved. However, the MOS-SCR triggered devices have more complicated structure that requires the device to have greater die area. These types of devices also require IC based manufacturing processes that requires many more masking steps (about 2×-3×) as compared to a DMOS type of process thus resulting in higher production costs.
In another co-pending patent application Ser. No. 11/982,526 previously submitted on Nov. 1, 2007, the Applicant of this invention further disclosed another improved TVS device structure to have an improved clamping at a further reduced voltage that TVS protection can be provided for devices operated at a voltage below 5 volts. The TVS protection circuit is implemented with a potential barrier based TVS structure thus providing simplified configuration for manufacturing the TVS device with simple DMOS type process without requiring the more expensive and complicated IC processes. Even with a lower triggering voltage disclosed in this application, further device protections for triggering voltage below 2.5 volts are still necessary. Additionally, there are concerns with the reliability of JFET based potential barrier triggering mechanism.
For better understanding of this invention, the descriptions of the FIGS. 3A to 3B from patent application Ser. No. 11/712,317 below are provided as background reference information of the TVS disclosed previously submitted and assigned to a common assignee of this Application.
FIG. 3A is a circuit diagram for showing a TVS as an exemplary embodiment of a prior art invention that implements a trigger circuit 180 for providing signal for triggering a main clamp circuit 190. The trigger circuit 180 includes four stacked PMOS transistors 181-1 to 181-4 with body effect wherein each PMOS transistor provide the option to have its body region tied to its source or to Vcc to create a reverse bias between its source and body that would increase the gate threshold voltage. By adjusting the number of PMOS transistor and the options of connecting the body of the PMOS transistors to its source or Vcc, the trigger voltage can be adjusted. In normal operation voltage, the stacking PMOS 181-1 to 181-4 are off because Vcc is not high enough to turn on the stacking PMOS transistors and therefore there is no current passing through resistor 182. The gate voltage of the NMOS 186 is low and below its threshold voltage and the NMOS 186 is turned off because the there is no current passing through the resistor 182 that is connected across the gate and the source of the NMOS transistor 186. The CMOS transistors, e.g., the PMOS 184 and the NMOS 185, has a low output voltage since the Vcc on the CMOS gate turns on the NMOS 185 but turns off the PMOS 184 and the output of the CMOS is connected to the ground through NMOS 185. The low voltage output turns off the trigger NMOS transistor 191 thus turns off the main clamp circuit.
Once a voltage transient event takes place, the voltage imposed onto the stacked PMOS 181-1 to 184-4 exceeds the sum of gate threshold voltages that turns on all of the stacked PMOS transistors causing a current to pass through the resistor 182. When this transient voltage is high enough and exceeds the trigger voltage which is equivalent to the sum of all the stacked PMOS threshold plus the threshold of NMOS 186, the current passing through the stacked PMOS and resistor 182 will increase until the voltage across the gate of the transistor 186 reach its threshold which consequently turns on the transistor 186. Once the transistor 186 conducts then the current passes through the resistor 183 and NMOS 186 to the ground. The ground voltage thus applied to CMOS gate turns off the NMOS 185 and turns on the PMOS 184 and the output voltage of CMOS is pulled up to Vcc thus triggers the main clamp circuit 190. FIG. 3B shows the output voltage of the trigger circuit 180 versus the input voltage Vcc. In FIG. 3B, the curve 287 corresponds to the trigger circuit output with three PMOS with body effect and line 288 corresponds to the trigger circuit output with four PMOS with body effect. The trigger voltage changes from about 3 Volts to 5 Volts as the number of stacked PMOS transistor increases from three to four. Below the trigger voltage, the output of trigger circuit 180 is zero volts while it increases linearly as the input voltage Vcc exceeds the designated trigger voltage. In normal working voltage range, the leakage current of trigger circuit 180 is also reduced. FIG. 3C shows the leakage current of trigger circuit 180 verses input voltage Vcc. At normal working voltage of 3.3 Volts, the leakage current is only tens of nano Amps, compare to a Zener diode triggered at similar voltage which has a leakage of micro Amps, one to two order of magnitude improvement is achieved.
With the trigger NMOS 191 turned on, the current passes through the resistor 193 and NMOS 191 and as the current increases so is the voltage drop across the emitter base junction of the PNP bipolar junction transistor (BJT). When the drop in the resistor 193 reaches a voltage of 0.6V then the base-emitter junction of the PNP transistor 194 is forward biased and the PNP transistor 194 turns on. Now the collector current of the PNP transistor flows through the resistor 195 connected between the emitter and base of the NPN transistor 192. When the potential drop in this resistor 195 reaches a voltage of 0.6V then the emitter of the NPN transistor 192 begins to conduct and a SCR mode operation is initiated. A protection diode 187 connecting between the CMOS output and ground is optional in case a high voltage surge is coupled into the CMOS output through a gate drain capacitor of trigger NMOS 191.
Therefore, the main clamp circuit 190 is a MOS trigger SCR that comprises a trigger NMOS 191 connected in series with a resistor 193 in parallel to a PNP bipolar transistor 194. The threshold voltage, of the triggering NMOS 191 is less than or equal to the BVceo of the PNP bipolar transistor 194 where BVceo stands for collector to emitter breakdown voltage with the base left open.
However, as pointed out earlier, this prior art requires several NMOS & PMOS transistors to implement the trigger circuit, and the MOS gated SCR. This requires the use of a standard CMOS process for fabrication and a large die to layout all the transistors and resistors in the circuit. In addition, the trigger circuit has many stages, which may affect the overall response time of the TVS circuit: This brings out the need for implementing a simpler device structure that achieves low voltage trigger and clamping and requires a simple fabrication process.
Therefore, a need still exists in the fields of circuit design and device manufactures for providing a new and improved circuit configuration and manufacturing method to resolve the above-discussed difficulties. Specifically, a need still exists to provide new and improved TVS circuits that can perform good voltage clamping function, occupying smaller areas and eliminating or reducing snapback voltage variations at a further reduced voltage down to a level below 2.5 volts to five volts for reliable protection of device operated at lower voltage level.